Integrated circuits (ICs) are known to comprise a limited number of logic circuits, a data bus and a serial port. As is known, internal points of an IC are tested after manufacturing to insure proper functionality. This is typically done by introducing test vectors into the IC and probing output pins along the IC for an expected result. While this method is effective, it only allows testing of those parts of the IC directly and indirectly accessible from the outside of the IC via the IC pins. Also, some parts of the IC cannot be practically tested due to the substantial number of test vectors needed to probe these parts of the IC. Further, the possibility exists than an expected response could be generated by more than one section of the logic circuit leading to ambiguous test results. Still further this method of testing only accommodates static testing; i.e. a test vector is given to the logic circuit and then, at a known time, the output pin is probed for the response.
Therefore, a need exists for an improved IC and method of testing logic circuits within the IC that is more comprehensive, efficient, and allows dynamic monitoring of the IC.